1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Miniaturization of semiconductor devices is making significant progress. The miniaturization, in turn, is promoting multilayer wiring structures. A multilayer wiring structure suffers from parasitic capacitance (to be referred to as a “line-to-line capacitance”) between upper and lower lines via an interlayer dielectric film. Image sensors, particularly CMOS image sensors, need to shorten the distance from the light-receiving surface of a photoelectric conversion element in each pixel to a microlens above the photoelectric conversion element to prevent degradation of optical characteristics when the pixel pitch is decreased. Along with this, an interlayer dielectric film interposed between the photoelectric conversion element and the microlens becomes thinner, increasing the line-to-line capacitance.
To solve this, Japanese Patent Laid-Open No. 5-36841 describes formation of a space 6 around a first-layer wiring structure 4. More specifically, after forming the first-layer wiring structure 4, a SiN film 1 is formed to cover the first-layer wiring structure 4. Further, a SiO2 film 2 is formed to cover the SiN film 1. A small hole 7 is formed in the SiO2 film 2 at a portion above the first-layer wiring structure 4. A space 6 is formed around the first-layer wiring structure 4 by dry etching through the small hole 7 using a CF4/O2 gas mixture. A spin-on-glass film 3 is then formed and sintered to cover the SiO2 film 2. At this time, the spin-on-glass film 3 does not enter the space 6 through the small hole 7 because of high surface tension. Thus, the small hole 7 can be closed while maintaining the space 6 around the first-layer wiring structure 4. According to Japanese Patent Laid-Open No. 5-36841, the line-to-line capacitance can be greatly reduced by forming the space 6 around the first-layer wiring structure 4.
In the arrangement disclosed in Japanese Patent Laid-Open No. 5-36841, as a second-layer wiring structure 5 becomes longer, the space 6 also becomes longer, decreasing the mechanical strength of the wiring structure. This wiring structure may be deformed or broken by CMP (Chemical Mechanical Polishing) in a subsequent step.